IDT82V3355EDG【PDF 7/135 页】IC PLL WAN SYNC ETHERNET 64TQFP

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3页 4页 5页 6页 [7页]8页 9页 10页 11页

IDT82V3355

SYNCHRONOUS ETHERNET WAN PLL

Programming Information

104

May 19, 2009

6.2.8

OUTPUT CONFIGURATION REGISTERS

OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration

Address: 6DH

Type: Read / Write

Default Value: 00001000

Bit

Name

Description

7 - 4

OUT2_PATH_SEL[3:0]

These bits select an input to OUT2.

0000 ~ 0011: The output of T0 APLL. (default: 0000)

0100: The output of T0 DPLL 77.76 MHz path.

0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.

0110: The output of T0 DPLL 16E1/16T1 path.

0111: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path.

1000 ~ 1011: The output of T4 APLL.

1100: The output of T4 DPLL 77.76 MHz path.

1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.

1110: The output of T4 DPLL 16E1/16T1 path.

1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.

3 - 0

OUT2_DIVIDER[3:0]

These bits select a division factor of the divider for OUT2.

The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output

(selected by the OUT2_PATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0/T4 DPLL outputs,

please refer to Table 25 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to

Table 26~T able 27 for the division factor selection.

76543210

OUT2_PATH_S

EL3

OUT2_PATH_S

EL2

OUT2_PATH_S

EL1

OUT2_PATH_S

EL0

OUT2_DIVIDER

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